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  • Welcome New Members

    I see a lot of you have joined this forum in the last several days. Please feel free to comment and spur discussion. If you would like a specific topic addressed let us know. There are 4 active developers for this spec and it is coming along nicely. Our goal is to present it to the RISC-V Foundation and to Khronos. Then we will socialize it within the RISC-V community. Eventually we will build an RTL model and test it in an FPGA and then fabricate an ASIC.

  • #2
    So happy to have discovered this!

    If we eventually reach the point where we've defined an architecture in RTL, would it not be a good idea to get into the Google Skywater lottery? I could probably reach out to Matthew Venn, who has been actively proselytizing the Google Skywater shuttle for some time now.

    Looking forward to learning more about the specification and seeing what comes of it!

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    • #3
      Thank you, yes we are actively working on the spec. We are also working on an LLVM back-end and a toolchain set up in Docker. Once we are comfortable using that we will release it to the public. We have an initial ISA defined that extends the RISC-V Vector ISA. Indeed Google has created a placeholder for it within their RV64V verification Github page to host our ISA. Once we have a verified ISA we will work on developing an RTL model that can be implemented in an FPGA or ASIC.

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