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Developing a Software Model for RV64X

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  • Developing a Software Model for RV64X

    Our first task is to develop a software model for RV64X. We can implement this in QEMU as it now has a Vector extension and supports the RISC-V architecture. I believe the following source supports the vector ISA but need to confirm:


    https://github.com/romanheros/qemu/tree/master/hw


    Abel has done a fantastic job of reconciling the RISC-V Vector ISA with SPIR-V and OpenGL ES 2.0. We now need to take the spec and develop a software model for the added instructions and possible register file extensions.


    The following types of instructions will need to be created:
    1. Texture sampling w/LOD
    2. Frame Buffer ops (bit blits)
    3. Vector element swizzling
    4. Partial Derivatives
    5. LOD selection

    Abel is working on a spec for the microarchitecture of the texture unit. We will need to develop RTL from that.


  • #2

    For our next meeting we would like to have a volunteer who can review:


    - What are the available RISC-V V simulators.
    - Qemu
    - Gem5


    - Toolchain support, is there an assembler?
    - Gcc for RISC-V may support the vector ISA

    - Is there an LLVM backend with support for vector registers?
    - Yes


    All those points need to be sorted out in order to start translating some GLSL programs into working code.

    Comment


    • #3
      I can look at that a bit. I've been reading about llvm, so I'm still very green, but I'll do what I can.

      Comment


      • azafar
        azafar commented
        Editing a comment
        Thank you so much Peter. We will have a call on Wednesday to discuss next steps!
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