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OpenGL ES 2.0 and a Fused CPU-GPU ISA for RV64X

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  • OpenGL ES 2.0 and a Fused CPU-GPU ISA for RV64X

    The first version of RV64X is targeted at supporting an OpenGL ES 2.0 feature set. This means that the fixed function transform and lighting and pixel processing of OpenGL ES 1.0+ is replaced by programmable shaders for the geometry/lighting/fragment operations with some severe limitations as compared to an OpenGL desktop implementation. A good reference for these features is found here:


    A good description of the geometry pipeline is here:

    and Rasterization (using Barycentric Coordinates)


    The following article from Daniel Koch and Nicolas Capens describes Angle, an emulation layer that implements OpenGL ES 2.0 on top of Direct3D

    GLSL functionality is described here:

    An excellent reference for the OpenGL ES 2.0 state machine is here:


    In RV64X, the GLSL virtual machine is replaced by the RISC-V Vector ISA, which is far more flexible and expansive than GLSL, so much more functionality is possible.

    For the Rasterizer Unit in RV64X we consider the rasterization of points, lines and triangles. So instructions for the following could be included:

    1. Accessing a linear frame buffer with a specified format for rendering a point with specific properties - color, size, multisample mode, texture etc.
    2. Rasterizing a line/vector/edge using a modified Bresenham Algorithm
    3. Rasterizing a triangle using Barycentric Interpolation

    So we will need instructions for:

    1. Linear FB access (Addr = Base + XSIZE * (y-1) + x)
    2. Bresenham parameter calculation (dx=x2-x1, dy=y2-y1, D=2*dy-dx)
    3. Barycentric parameter calculation ((yayb)x+(xbxa)y+xaybxbya)

    There are inherent advantages to NOT limiting shader programs to a standard GLSL virtual machine. In OpenGL ES 2.0, branches are only in the forward direction and there are limits on shader program size etc. By using a RISC-V Vector core as the shader "CPU", MIMD (as opposed to SIMT) shader architectures are possible. This opens up all kinds of possibilities for graphics, physics, AI and other applications.

    For example, it would be easy to implement ray-tracing on this architecture because one shader core could do the intersection calculations, while another computes lighting while yet another computes material interactions and physics, all in a MIMD processor arrangement. Furthermore, a unified memory architecture can permit all cores to share the same intermediate data, with perhaps a transactional memory model.

    Some of the possibilities such an architecture could enable are described in my blog here:
    Attached Files

  • #2
    A while back when we discussed SIMD vs Vector, I found this interesting read:

    I think the Fused CPU-GPU goal of RV64X follows nicely from the article.


    • azafar
      azafar commented
      Editing a comment
      Yes, I have seen this article before also - very nice! When I presented the idea of a fused CPU-GPU ISA at the RISC-V meeting @ Western Digital (in Milpitas) in the fall of 2019 I got a standing ovation from the audience. So I think that is one of our advances as NO GPU vendor has that yet! It also greatly simplifies the memory architecture and provides for a unified memory architecture design